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[Other] SOC-design-and-IP-core-reuse

Description: SOC设计与IP核重用技术 SOC design and IP core reuse-SOC design and IP core reuse
Platform: | Size: 21548032 | Author: wefweff | Hits:

[Com Port] uart-IP-Core

Description: 串口的FPGA VHDL的IP核 可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
Platform: | Size: 322560 | Author: 吴星 | Hits:

[VHDL-FPGA-Verilog] 8051-IP-Core

Description: 8051的IP核，可以使用FPGA IP节点导入此IP核，实现单片机的功能。-8051 IP core can be used the FPGA IP node to import this IP core microcontroller functions.
Platform: | Size: 410624 | Author: 吴星 | Hits:

[Software Engineering] crc-ip-core-usage

Description: CRC 编译码IP核的使用方法，仿真图和matlab的结果对比对比，fpga编程时使用-CRC encoding and decoding IP core use simulation in Fig the Matlab results contrast contrast
Platform: | Size: 65536 | Author: 火山灰 | Hits:

[VHDL-FPGA-Verilog] viterbi-ip-core-using-mothed

Description: FPGA的Viterbi译码器IP 核的使用说明，简单方便，一目了然。还能进行tcm译码，功能强大呀-Instructions for use of the FPGA Viterbi decoder IP core, easy glance. Can tcm decoding powerful!
Platform: | Size: 54272 | Author: 火山灰 | Hits:

[VHDL-FPGA-Verilog] verilog-ip-core

Description: verilog ip核，源代码，ethernet， video_compression_systems-verilog ip core source code, ethernet, video_compression_systems
Platform: | Size: 3798016 | Author: 刘兵 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM-Verilog-HDL-IP-CORE

Description: ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。-ARM processor IP core, written in verilog processor and CPU architecture knowledge.
Platform: | Size: 74752 | Author: shen jun | Hits:

[ARM-PowerPC-ColdFire-MIPS] 8051-IP-core

Description: 这个整体的代码是8051的IP核，相信对于学习处理器和CPU架构的朋友，都会有很大帮助。-The overall code 8051 IP core, I believe that learning processor and CPU architectures friends, there will be a great help.
Platform: | Size: 292864 | Author: shen jun | Hits:

[VHDL-FPGA-Verilog] ARM-Verilog-HDL-IP-CORE

Description: ARM Verilog HDL IP CORE， ARM IP核，采用verilog编写-ARM Verilog HDL IP CORE, ARM IP core, using verilog write
Platform: | Size: 48128 | Author: xuyanwu | Hits:

[Other] Altera-SDRAM_controller-IP-CORE

Description: Altera的SDRAM IP核代码，支持源码创作-Altera s SDRAM IP core code to support the creation of source
Platform: | Size: 3500032 | Author: chen600 | Hits:

[VHDL-FPGA-Verilog] WISHBONE-Interconnect-Matrix-IP-CORE

Description: 来自opencores.org 开源IP 很好的资料，供大家学习-WISHBONE Interconnect Matrix IP CORE
Platform: | Size: 106496 | Author: 程硕 | Hits:

[VHDL-FPGA-Verilog] Creating-Project-and-IP-Core-in-ISE

Description: 本文介绍了在ISE环境中如何新建工程，并且定义设置IP核进行开发-This article describes how new construction ISE environment, and define the settings IP core development
Platform: | Size: 678912 | Author: aj | Hits:

[VHDL-FPGA-Verilog] grey-code--FIFO-IP-core

Description: 基于格雷码的FIFO的IP核，调试可用于通信接口的队列传输。-Gray code based on FIFO IP core, debugging can be used for communication queue transmission interface.
Platform: | Size: 37888 | Author: 瞿盛 | Hits:

[VHDL-FPGA-Verilog] SPDIF-interface-IP-core

Description: SPDIF数字音频接口的的程序，已写成通用IP核形式。-The program SPDIF digital audio interface has been written in the form of common IP core.
Platform: | Size: 44032 | Author: 瞿盛 | Hits:

[VHDL-FPGA-Verilog] FPGA-IP-core

Description: FPGA中IP核的调用 适用于初学者,里面是两个PPT 其中一个主要讲RAM&ROM IP CORE的调用-usage of FPGA IP core ,Suitable for beginners
Platform: | Size: 8019968 | Author: 陈茂敬 | Hits:

[assembly language] CAN-IP-Core

Description: CAN IP Core can硬件的IP核，用于cpld和fpga编程can接口-CAN IP Core
Platform: | Size: 119808 | Author: liucl | Hits:

[Other] the-IP-IP-core-solution-of-ISE

Description: ISE IP核详细解释与使用方法，包括接口定义及如何使用列子-the IP IP core solution of ISE
Platform: | Size: 14923776 | Author: 施楠 | Hits:

[VHDL-FPGA-Verilog] mc8051_design

Description: 使用VHDL语言，实现C8051 IP Core(Use VHDL, Realize C8051 IP Core)
Platform: | Size: 407552 | Author: 飞雪漫天 | Hits:

[Other] SPWM信号产生系统IP软核设计及验证

Description: 针对电力电子领域的需求，采用自然采样法设计了一个全数字三相SPWM信号产生系统IP软核．通过数字频率合成技术实现了对电源频率的辅确控制．使电源频率精度达到16位．其中。通过调节控制参数．分别实现了电源频率与载波频率的7级、8级控制．最后。搭建了基于FPGA的测试系统．验证了系统功能的正确性．(According to the requirement of power electronics, the natural sampling method for the design of a full digital three-phase SPWM signal generation system. The power frequency of IP core is the auxiliary control is implemented through digital frequency synthesis technology. The power frequency accuracy of 16. By adjusting the control parameters, 7 and 8 levels of power frequency and carrier frequency are realized respectively. Finally, the control of the power frequency and carrier frequency is realized. A test system based on FPGA is built, which verifies the correctness of the system function)
Platform: | Size: 250880 | Author: 破劫 | Hits:

[VHDL-FPGA-Verilog] 不用IP核设计乘法器

Description: VerilogHDL语言实现 不用IP核设计乘法器。(VerilogHDL language, do not use IP core design multiplier.)
Platform: | Size: 405504 | Author: 朱朱8 | Hits:
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